In recent years, with development of portable terminals, speeding up of data processing has become essential, so that speeding up of computation processing of RISC CPUs mounted on portable terminals is also required. When compression and expansion of a photograph image (in JPEG format) is performed in the portable terminal, for example, a DCT (Discrete Cosine Transform)/quantitization/inverse-quantitization techniques are employed. Speeding up of multiplication is then required.
Generally, for the multiplication by the RISC CPU, there are provided a method of using a barrel shifter and an adder and a method of using a multiplier. A program compiler makes a decision as to which method is faster according to a multiplier, and determines the method. The case where the multiplication is executed using the barrel shifter and the adder is the case where a multiplier factor 2m+1 (m≧1) is applied on a certain number A, for example. In this case, the certain number A is shifted in the left by m bits by the barrel shifter to produce 2m·A. Then, 2m·A+A is executed by the adder to obtain the solution. Since the latencies of the barrel shifter and the adder of the RISC CPU are generally one clock cycle, respectively, the latency of this multiplication becomes two clock cycles. The latency of the multiplier is three clock cycles. Thus, if the barrel shifter and the adder are used, the multiplication can be performed faster by one clock cycle than in the case where the multiplier is used.
In ARM CPUs, the barrel shifter and the adder are connected in series so that the multiplication is executed in one clock cycle. Then, the latency in the method of using the barrel shifter and the adder is thereby reduced to achieve speeding up of the multiplication. The multiplication described before can be thereby implemented in one clock cycle. Further, the multiplication in which the multiplier factor applied on the certain number A is 2m+n+2m+2n+1 =(2m+1)(2n+1) can also be implemented in two clock cycles.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2000-163251A